1. Field of the Invention
The present invention relates to a constant current controller, especially to a constant current controller for constant current power modules.
2. Description of the Related Art
FIG. 1 illustrates a circuit diagram of a prior art constant current power module. As illustrated in FIG. 1, the prior art constant current power module includes a transformer 10, an NMOS transistor 20, a resistor 30, a controller 40, a diode 51, a capacitor 52, resistors 53, 54, capacitors 55, 56, a resistor 57, a diode 60, a capacitor 70, and a load 80.
The transformer 10 has a primary coil of NP turns, a secondary coil of NS turns, and an auxiliary coil of NA turns.
The NMOS transistor 20 is used for controlling a primary side current IP flowing through the primary coil according to a duty ratio of a gate signal VG.
The resistor 30, connected between the NMOS transistor 20 and a ground, is used for generating a current sensing signal VCS in response to the primary side current IP.
The controller 40 is used for generating the gate signal VG in response to the current sensing signal VCS and a detection signal VDET.
The diode 51 and the capacitor 52, connected between the auxiliary coil and the ground, are used to regulate an auxiliary signal VAUX from the auxiliary coil to generate a supply voltage for the controller 40.
The resistors 53, 54 are used to divide the voltage of the auxiliary signal VAUX to generate the detection signal VDET.
The capacitor 55, connected between a COMV pin of the controller 40 and the ground, is used for the frequency compensation of an error voltage amplification.
The capacitor 56, connected between a COMI pin of the controller 40 and the ground, is used for the frequency compensation of an error current amplification.
The resistor 57, connected between a COMR pin of the controller 40 and the ground, is used for cable loss compensation.
The diode 60 is used for releasing the magnetic energy of the transformer 10 in a form of a secondary side current IS when the NMOS transistor 20 is off.
The capacitor 70 is used for filtering the secondary side current IS to provide a regulated output current IO or regulated output voltage VO for the load 80.
A detailed function block diagram of the controller 40 is illustrated in FIG. 2. As illustrated in FIG. 2, the controller 40 has a V-LOOP unit 41 for detecting the voltage variation of the detection signal VDET to generate a discharging time signal SDS; an I-LOOP unit 42 for detecting a peak value of the current sensing signal VCS and providing an output voltage VW representing the peak value; a filter unit 43 for generating a filtered voltage VI according to VW and the discharging time signal SDS; and an amplifier 44 for amplifying the difference between a reference voltage VREF2 and the filtered voltage VI.
FIG. 3 illustrates a waveform diagram for the primary side current IP, the current sensing signal VCS, the secondary side current IS, the detection signal VDET, and the discharging time signal SUS, wherein the primary side current IP has a peak value IP-PEAK and a cycle period TS; the current sensing signal VCS has a peak value represented by VW; the secondary side current IS has a peak value IS-PEAK and a cycle-averaged value IS-cycle: and the detection signal VDET has a low-level period TON representing a primary side charging time, and a high-level period TDIS representing a secondary side discharging time.
A circuit diagram of the I-LOOP unit 42 is illustrated in FIG. 4. As illustrated in FIG. 4, the I-LOOP unit 42 includes a comparator 421, a current source 422, switches 423-425, and capacitors 426-427.
The comparator 421 has a positive input connected to the current sensing signal VCS, a negative input connected to the capacitor 426, and an output connected to the switch 423. When the voltage of the current sensing signal VCS is higher than that over the capacitor 426, the comparator 421 will output a high level to switch on the switch 423 so that the capacitor 426 is charged by the current source 422. When the voltage of the current sensing signal VCS is lower than that over the capacitor 426, the comparator 421 will output a low level to switch off the switch 423 so that a peak value of the current sensing signal VCS is stored on the capacitor 426. The charge on the capacitor 426 is than redistributed over the capacitor 426 and the capacitor 427 by a control signal PLS to provide the output voltage VW. A control signal CLR is then used to discharge the capacitor 426.
A circuit diagram of the filter unit 43 is illustrated in FIG. 5. As illustrated in FIG. 5, the filter unit 43 includes an amplifier 430, an NMOS transistor 431, PMOS transistors 432-433, a resistor 434, switches 435-437, and capacitors 438-439.
The amplifier 430 has a positive input connected to the output voltage VW, a negative input connected to the resistor 434, and an output connected to the NMOS transistor 431. Due to a virtual short between the positive input and the negative input of the amplifier 430, the voltage across the resistor 434 will be approaching VW, and a current I432 equal to (VW/the resistance of the resistor 434) will be generated accordingly. The PMOS transistors 432-433 act as a current mirror to generate a current IPRG according to I432. The switch 435 is switched on by the discharging time signal SDS for a time equal to TDIS to charge the capacitor 438 with the current IPRG. The charge on the capacitor 438 is than redistributed over the capacitor 438 and the capacitor 439 by the control signal PLS to provide the filtered voltage VI. The control signal CLR is then used to discharge the capacitor 438.
Based on the foregoing descriptions, the principle of controlling the DC output current IO of the circuit in FIG. 1 is further explained as follows:
When the circuit of FIG. 1 is operating in DCM (discontinuous conduction mode), the peak value IS-PEAR of the secondary side current IS can be expressed as:IS-PEAK=(NP/NS)×IP-PEAK.As can be seen in FIG. 3, the secondary side current IS is of a triangle waveform, therefore, its cycle-averaged value IS-Cycle can be expressed as:IS-Cycle=IS-PEAK×(TDIS/2TS)=(NP/NS)×IP-PEAK×(TDIS/2TS).Both NP and NS are constant values. As the controller 40 of FIG. 1 adopts a fixed-frequency control mechanism, therefore, TS is also a constant value. The cycle-averaged value IS-cycle is then dependent on IP-PEAK×TDIS. IP-PEAK can be represented by VW/(the resistance of the resistor 30), and TDIS can be represented by the high level period of SDS.
By virtue of a virtual short between the positive input and negative input of the amplifier 44, VI will be regulated at the reference voltage VREF2, and the cycle-averaged value IS-Cycle will be held at a constant value. The expressions are as follows:VI=average of (IPRG×TDIS)/the capacitance of the capacitor 438=average of ((VW/the resistance of the resistor 434)×TDIS)/the capacitance of the capacitor 438=VREF2, andIS-Cycle=(NP/NS)×average of (IP-PEAK×TDIS)/2TS=(NP/NS)×average of (VW/(the resistance of the resistor 30)×TDIS)/2TS=(NP/NS)×(VREF2×the resistance of the resistor 434×the capacitance of the capacitor 438)/(2×the resistance of the resistor 30×TS).
In practical applications, the resistance of the resistor 434 and the capacitance of the capacitor 438 will have variations due to manufacturing processes. With an OSC unit (shown in FIG. 2) using same circuit architecture of FIG. 5 for determining TS, the variations of the resistance of the resistor 434 and the capacitance of the capacitor 438 can be compensated. However, the variations of TS will impact the power module on its EMI performance, efficiency performance, and its transformer selection. Although the mentioned problems can be tackled by trimming the resistance of the resistor 434 and the capacitance of the capacitor 438 in each power module, however, it will incur manufacturing cost and excess manufacturing procedures.
To solve the foregoing problems, a novel constant current controller is needed.